The present invention relates generally to semiconductor devices and more particularly to complementary insulated-gate field-effect transistors (CMOSs).
One of the conventional semiconductor devices is disclosed, e.g. in JP-A 58-201353. This semiconductor device is constructed such that, when excessive surge or electrostatic discharge (ESD) voltage is applied to an input/output terminal, the existence of an N.sup.+ buried region formed to the bottom of an N-well contributes to a reduction in the current amplification factor h.sub.PE of a PNP bipolar transistor, and a shunt resistance between the emitter and the base thereof. This results in restrained latchup so called.
However, the above semiconductor device has the following problems:
First, due to reduced capacity of the PNP bipolar transistor to bypass ESD current, ESD current is concentrated on one of the pull-up and pull-down diodes in a protective element, resulting in lowered breakdown strength of the semiconductor device with respect to ESD current;
Second, due to high-temperature annealing of the semiconductor device during a fabrication process, N-impurities within the N.sup.+ buried region can be diffused in the upper portion thereof to increase the surface concentration of N-impurities in the N-well. This reduces breakdown voltage of a P-channel insulated-gate field-effect transistor (PchMOSFET) formed in the principal surface of the N-well, resulting in difficult control of a threshold value thereof; and
Third, due to reduced on-resistance of a lateral power transistor formed in another N-well, the N.sup.+ buried region cannot show sufficiently high concentration of N-impurities. If two N.sup.+ buried regions are formed separately, the fabrication process of the semiconductor device will be complicated, resulting in increased manufacturing cost.
It is, therefore, an object of the present invention to provide semiconductor devices which show improved anti-latchup characteristic and sufficiently reduced on-resistance of a power transistor with cheaper manufacturing cost.